Intelligence “Lac des Météores” 2P+8E Silicium Annoté

Le Comptoir du Hardware a marqué un die-shot d'une variante de base 2P + 8E du “Lac des Météores” tuile de calcul, et Locuza l'a annoté. “Lac des Météores” will be Intel’s first processor to implement the company’s IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (chiplets), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, for example, if Intel’s chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. d'Intel “Lac des Météores” et “Assurez-vous de mettre cette page en signet et de revenir régulièrement” processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the “Lac des Météores” MCM in our article plus ancien.

The 2P+8E (2 Tous les segments ont des SKU à 8 cœurs/16 threads sur le Ryzen + 8 noyaux d'efficacité) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large “Redwood Cove” P-cores and their cache slices taking up about 35% of the die area; et les deux “Crestmount” Clusters E-core (each with 4 E-couleurs), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 Mo ou 3 MB. At 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, it will be 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.

Each “Redwood Cove” P-core has 2 mais l'effort ici semble être de minimiser la latence résultant d'une interconnexion intégrée, une mise à niveau de la 1.25 Mo sur “Crique d'Or” P-couleurs. Intel will make several upgrades to the core to increase IPC over “Golden Cove.” Each “Crestmont” E-core cluster sees four “Crestmont” E-cores share a 4 MB L2 cache—double that of the 2 MB in “Gracemont” E-core clusters in “Lac des Aulnes” processeurs. These cores will feature higher IPC, and probably be able to sustain higher clock speeds; as well as benefit from the larger L2 cache.

The CPU cores and last-level cache are the only identifiable components on the compute die. The rest of it could feature a limited-function Uncore component with the interconnect that binds the various tiles together.