AMD Makes 3DV Cache a Part of its Long-term Roadmap, Announces Genoa-X and Siena

AMD in its recent interview with TechPowerUp had asserted that 3D Vertical Cache (or 3DV Cache), isn’t a one-off technology and that it would be a continual part of its roadmap. In its 2022 Financial Analyst Day presentation, the company confirmed this, by announcing variants of its CPU chiplets that have 3DV Cache, extending to both the upcoming “Zen 4” microarchitecture, and the upcoming “Zen 5,” which it unveiled today.

EPYC “Genoa” is codename for the upcoming line of server processors based on the “Zen 4” CPU microarchitecture, with CPU core-counts of up to 96-core/192-thread. These feature the standard “Zen 4” CCD. The company hasn’t yet announced the last-level cache (L3 cache) size of the standard “Zen 4” CCD. The company will launch the EPYC “Genoa-X” processor, which much like the EPYC “Milan-X,” will incorporate 3DV Cache, with a stacked L3 cache die on top of the chiplet. “Genoa-X” is slated for a 2023 debut.

“Genoa” and “Genoa-X” aren’t the only enterprise processors based on “Zen 4,” with the company already having announced the EPYC “Bergamo” processor with 128-core/256-thread core-count, meant for cloud-computing environments, based on the “Zen 4c” sub-variant that has certain cloud-relevant capabilities while retaining the full ISA of “Zen 4.” There’s yet another new processor being announced today, codenamed “Siena.”

The EPYC “Siena” processor (named after the Italian city, not the French river), is targeted at the telecommunications and edge-compute industry, and should cash in on the 5G infrastructure market growth. This chip comes with a lean 64-core/128-thread core-config, with an optimized performance/Watt, and possibly I/O best suited for 5G infrastructure. AMD is planning to launch the EPYC “Siena” in 2023.