AMD Ryzen 7000 “Phoenix” APUs with RDNA3 Graphics to Rock Large 3D V-Cache
AMD has used large caches to good effect both on its “Zen 3” processors, such as the Ryzen 7 5800X3D, where they’re called 3D Vertical Cache (3D V-cache); as well as its Radeon RX 6000 discrete GPUs, where they’re called Infinity Cache. The only known difference between the two is that the latter is fully on-die, while the former is stacked on top of existing silicon IP. It’s being reported now, that “Phoenix” will indeed feature a stacked 3D V-cache.
The exact function of this isn’t known—whether it serves as a last-level cache for the CPU or iGPU. AMD’s APU architecture differs from Intel’s processors that have iGPUs. On the Intel chips, the L3 cache serves as town-square for the entire SoC, with each IP block contributing an L3 cache slice that make up a functionally-contiguous cache that all IP blocks can equally address over the Ring Bus. On AMD APUs such as “Cezanne” or “Rembrandt,” the L3 cache is part of the CCX (CPU cores complex), and serves exclusively as last-level cache for the CPU cores. The iGPU has its own LLC, and the Infinity Fabric interconnect is the ether binding all IP blocks on the silicon.
The obvious direction for development in future APUs could be a unification of last-level cache for the CCX and iGPU, provided the cache is large enough for the function—and this can be accomplished by stacked cache. An RDNA2 GPU with performance rivaling the RTX 3060 Laptop GPU, the Radeon RX 6650M XT, based on the “Navi 23” silicon, has 32 MB of Infinity Cache. This means, with some clever cache memory-management, an LLC in the neighborhood of 64 MB could emerge feasible for the APU.