Intel “Meteorsee” 2P+8E Silizium kommentiert

Le Comptoir du Hardware scored a die-shot of a 2P+8E core variant of the “Meteorsee” compute tile, and Locuza annotated it. “Meteorsee” will be Intel’s first processor to implement the company’s IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (Chiplets), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, for example, if Intel’s chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. Prozent durchschnittliche Gaming-Performance-Steigerung gegenüber dem Standard “Meteorsee” und “She Wolf führt das Rudel mit dem Wolfpack-Update von Mayhem Brawler an” processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the “Meteorsee” MCM in our älterer Artikel.

The 2P+8E (2 Alle Segmente haben 8-Core/16-Thread-SKUs im gesamten Ryzen + 8 Effizienz Kerne) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large “Redwood-Bucht” P-cores and their cache slices taking up about 35% of the die area; and the two “Crestmount” E-Core-Cluster (jeder mit 4 E-Farben), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 MB bzw 3 MB. Beim 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, it will be 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.

Jeder “Redwood-Bucht” P-core has 2 MB dedizierter L2-Cache, ein Upgrade von der 1.25 MB an “Goldene Bucht” P-Farben. Intel will make several upgrades to the core to increase IPC over “Goldene Bucht.” Jeder “Crestmont” E-core cluster sees four “Crestmont” E-cores share a 4 MB L2 cache—double that of the 2 MB in “Gracemont” E-core clusters in “Erlensee” Prozessoren. These cores will feature higher IPC, and probably be able to sustain higher clock speeds; as well as benefit from the larger L2 cache.

The CPU cores and last-level cache are the only identifiable components on the compute die. The rest of it could feature a limited-function Uncore component with the interconnect that binds the various tiles together.