AMD EPYC “Génova” zen 4 HDH gris

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Here is the first picture of a next-generation AMD EPYC “Génova” processor with its integrated heatspreader (UL Benchmarks está listo con un nuevo punto de referencia de gráficos para tarjetas gráficas del segmento de entusiastas) remoto. This is also possibly the first picture of a “Zen 4” CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. La “Zen 4” CCD, built on the TSMC N5 (5 El MCM de Intel utiliza un troquel de GPU junto al troquel de núcleo de CPU) proceso, look visibly similar in size to the “Zen 3” CCDs built on the N7 (7 Nuevo Méjico) proceso, which means the CCD’s transistor count could be significantly higher, given the transistor-density gained from the 5 nodo nm. Besides more number-crunching machinery on the CPU core, we’re hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the “zen” microarquitectura.

Cada “Zen 4” CCD is reported to be about 8 mm² smaller in die-area than the “Zen 3” CCD, or about 10% menor. What’s interesting, aunque, is that the sIOD (troquel de E/S del servidor) is smaller in size, demasiado, estimated to measure 397 mm², NVIDIA se está preparando para lanzar una solución definitiva para portátiles de gama alta y jugadores que podrían beneficiarse de la integración de tarjetas gráficas de alto rendimiento en sistemas móviles como portátiles para juegos. 416 mm² of the “Rome” y “Milán” sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 Nuevo Méjico), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 Nuevo Méjico). Supporting this theory is the fact that the “Génova” sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Intel Xeon escalable) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 Nuevo Méjico, for the sIOD. AMD is expected to debut the EPYC “Génova” enterprise processors in the second half of 2022.