Microsoft Azure se une a Intel Foundry Services Cloud Alliance
This is the latest chapter in a partnership between Intel and Microsoft that stretches back decades all the way back to the early days of the personal computer. In the last few years, Intel and Microsoft have collaborated on advancing semiconductor design on the cloud by working together to bring out EDA centric cloud compute such as the FX series on Azure, working with EDA vendors to enhance their software to better take advantage of the elasticity of the Azure cloud, as well as collaborating on a secure cloud-based semiconductor development platform for the US Department of Defense RAMP and RAMP-C programs.
IFS will also partner with Microsoft and NetApp to host a Microsoft Azure booth at the Design Automation Conference later this year in San Francisco. Working together, Intel and Microsoft will develop best practices and optimal guidelines to help customers leverage the capabilities of the Azure cloud for chip design. This alliance will result in proven flows and methodologies targeting Intel foundry collateral and process design kits (PDKs). Customers will see Microsoft Azure provide a secure design environment for semiconductor design and enhanced capabilities for design teams to securely collaborate with EDA vendors and other partners.
This alliance will provide fabless semiconductor companies of all sizes with the capability to design and target advanced node silicon processes. By leveraging the performance and scale provided by Azure, small and medium fabless companies will be able to address designs complexity that would have been challenging with on-prem infrastructure. Large fabless companies can also benefit by being able to target Intel advanced process nodes while supplementing their on-prem resources with newer cloud-based resources and EDA tools optimized to run on the cloud.
A través de esta colaboración, we look forward to providing the industry with the capability to access newer nodes, achieve more efficient chip design, higher coverage, lower tape-out risk and improve first silicon success.