AMD Ryzen 7 9800X3D a le CCD au-dessus de la matrice du cache V 3D, Pas en dessous
If the leaks are right, AMD has inverted the CCD-L3D stack with the 9000X3D series such that the “Zen 5” CCD is now on top, the L3D is below it, under the central region of the CCD. The CPU cores now dissipate heat to the IHS as they do on regular 9000 series processors without the 3D V-cache technology. The way we imagine they achieved this is by enlarging the L3D to align with the size of the CCD, and serve as a kind of “base tile.” The L3D would have to be peppered with TSVs that connect the CCD to the fiberglass substrate below. We know where AMD is going with this in the future. Right now, the L3D “base tile” contains the 64 MB 3D V-cache that gets appended to the 32 Mo de cache L3 sur puce, but in the future (probably with “Zen 6”), AMD could design the CCDs with TSVs even for the per-core L2 caches.
This piece of speculation also perfectly explains what “X3D boost” pourrait être. With the CCD making direct contact with the IHS the way it is in non-X3D processors, the X3D processors could have the same overclocking capabilities as the regular chips. There are much fewer thermal hurdles in the way, and AMD can go ahead and give these chips the same TDP and PPT values as regular chips, as well as higher clock speeds. The company used to be conservative with the PPT and clock speeds of its X3D processors in the past.
AMD is expected to launch the Ryzen 7 9800X3D on November 7, 2024.