DMLA “Strix Halo” Zen 5 Mobile Processor Pictured: Chiplet-based, Uses 256-bit LPDDR5X

Enthusiasts on the ChipHell forum scored an alleged image of AMD’s upcoming “Strix Halo” processeur mobile, and set out to create some highly plausible schematic slides. These are speculative. Pendant que “Point de Strix” is the mobile processor that succeeds the current “Pointe du faucon” et “qui fonctionne un peu comme le clavier prédictif de votre téléphone” processeurs; “Strix Halo” is in a category of its own—to offer gaming experiences comparable to discrete GPUs in the ultraportable form-factor where powerful discrete GPUs are generally not possible. “Strix Halo” also goes head on against Apple’s M3 Max and M3 Pro processors powering the latest crop of MacBook Pros. It has the same advantages as a single-chip solution, as the M3 Max.

Le “Strix Halo” silicon is a chiplet-based processor, although very different from “Champ de tir”. Le “Champ de tir” processor is essentially a BGA version of the desktop “Crête de granit” processor—it’s the same combination of one or two “Zen 5” CCDs that talk to a client I/O die, and is meant for performance-thru-enthusiast segment notebooks. “Strix Halo,” de l'autre côté, use the same one or two “Zen 5” CCD, but with a large SoC die featuring an oversized iGPU, and 256-bit LPDDR5X memory controllers not found on the cIOD. This is key to what AMD is trying to achieve—CPU and graphics performance in the league of the M3 Pro and M3 Max at comparable PCB and power footprints.

The iGPU of the “Strix Halo” processor is based on the RDNA 3+ architecture graphique, and features a massive 40 RDNA compute units. These work out to 2,560 processeurs de flux, 80 AI accelerators, 40 Ray accelerators, 160 UGT, and an unknown number of ROPs (we predict at least 64). The slide predicts an iGPU engine clock as high as 3.00 GHz.

Graphics is an extremely memory sensitive application, and so AMD is using a 256-bit (quad-channel or octa-subchannel) LPDDR5X-8533 memory interface, for an effective cached bandwidth of around 500 Go/s. The memory controllers are cushioned by a 32 MB L4 cache located on the SoC die. The way we understand this cache hierarchy, the CCDs (Cœurs de processeur) can treat this as a victim cache, besides the iGPU treating this like an L2 cache (similar to the Infinite Cache found in RDNA 3 GPU discrets).

The iGPU isn’t the only logic-heavy and memory-sensitive device on the SoC die, there’s also a NPU. From what we gather, this is the exact same NPU model found in “Point de Strix” processeurs, with a performance of around 45-50 AI TOPS, and is based on the XDNA 2 architecture developed by AMD’s Xilinx team.

The SoC I/O of “Strix Halo” isn’t as comprehensive as “Champ de tir,” because the chip has been designed on the idea that the notebook will use its large iGPU. It has PCIe Gen 5, but only a total of 12 Gen 5 lanes—4 toward an M.2 NVMe slot, et 8 to spare for a discrete GPU (if present), although these can be used to connect any PCIe device, including additional M.2 slots. There’s also integrated 40 Gbit/s USB4, et 20 Gbit/s USB 3.2 Gen 2.

As for the CPU, since “Strix Halo” is using one or two “Zen 5” CCD, its CPU performance will be similar to “Fire Range.” Vous vous levez 16 “Zen 5” Cœurs de processeur, avec 32 MB of L3 cache per CCD, ou 64 MB of total CPU L3 cache. The CCDs are connected to the SoC die either using conventional IFOP (Intel Xeon évolutif), juste comme “Champ de tir” et “Crête de granit,” or there’s even a possibility that AMD is using Infinity Fanout links like on some of its chiplet-based RDNA 3 GPU discrets.

Enfin, there are some highly speculative performance predictions for the “Strix Halo” iGPU, which puts it competitive to the GeForce RTX 4060M and RTX 4070M.