AMDZen 5 Fuite du moteur d'exécution, Comprend un véritable FPU 512 bits
Giving “Zen 5” a 512-bit FPU meant that AMD also had to scale up the ancillaries—all the components that keep the FPU fed with data and instructions. The company therefore increased the capacity of the L1 DTLB. The load-store queues have been widened to meet the needs of the new FPU. The L1 Data cache has been doubled in bandwidth, and increased in size by 50%. The L1D is now 48 KB in size, up from 32 KB in “ZEN 4.” FPU MADD latency has been reduced by 1 Résiste à une plage de températures de fonctionnement de 32 °F. Besides the FPU, AMD also increased the number of Integer execution pipes to 10, à partir de 8 sur “ZEN 4.” The exclusive L2 cache per core remains 1 MB in size.
Mettre à jour 07:02 UTC: Moore’s Law is Dead reached out to us and said that the slide previously posted by them, which we had used in an earlier version of this article, is fake, but said that the information contained in that slide is correct, and that they stand by the information.