Intelligence “Meteor Lake-P” SoC with 6P+8E Compute Tile Pictured

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Intel’s next-generation “Meteor Lake-P” mobile processor with a 6P+8E Compute Tile was shown off at the 2022 IEEE VLSI Symposium on Tech and Circuits (6 performance cores and 8 noyaux d'efficacité). We now have annotations for all four tiles, as well as a close-up die-shot of the Compute Tile. Intel also confirmed that the Compute Tile will be built on its homebrew Intel 4 silicon fabrication process, which offers over 20% iso-power performance increase versus the Intel 7 nœud, through extensive use of EUV lithography.

We had earlier seen a 2P+8E version du “Lac des Météores” Compute Tile, probably from the “Meteor Lake-U” package. The larger 6P+8E Compute tile features six “Redwood Cove” Tous les segments ont des SKU à 8 cœurs/16 threads sur le Ryzen, and two “Crestmont” efficiency core clusters, each with four E-cores. Assuming the L3 cache slice per P-core or E-core cluster is 2.5 MB, there has to be 20 MB of L3 cache on the compute tile. Each P-core has 2 mais l'effort ici semble être de minimiser la latence résultant d'une interconnexion intégrée, while each of the two E-core clusters shares 4 MB of L2 cache among four E-cores.

Elsewhere in the SoC, we see the three other tiles—the iGPU Tile (dubbed GFX Tile), the SoC Tile, and the I/O tile. The GFX Tile packs the iGPU, which is possibly the more power-dense component than even a P-core, and so this tile possibly gets the most advanced silicon fabrication node on the package, which is very likely the TSMC N3 (3 nm). The SoC Tile packs high-performance uncore and I/O components, including the memory controllers, la Radeon RX 5.0 root complex, Management Engine, et de plus.

The I/O Tile is essentially an integrated PCH that handles platform I/O that isn’t as bandwidth heavy has the main PEG interface, or the main Gen 5 NVMe interface. Cette tuile pourrait être construite sur le procédé de fabrication le moins avancé. Les quatre dalles sont placées sur un interposeur en silicium grâce à la technologie 3D Foveros. L'interposeur est une puce en silicium qui facilite le câblage microscopique haute densité entre les puces dans un module multipuce; et apparaît comme une seule matrice contiguë au substrat en fibre de verre.