Samsung développe la norme de mémoire GDDR6W: Doublez la bande passante et la densité de GDDR6 grâce à des innovations d'emballage
This is the central idea behind one of the most popular concepts in virtual reality: Double digitale. A digital twin is a virtual representation of an object or space. Updated in real-time in accordance with the actual environment, a digital twin spans the lifecycle of its source and uses simulation, machine learning and reasoning to help decision-making. While until recently this was not feasible proposition due to limitations on data processing and transference, digital twins are now gaining traction thanks to availability of high bandwidth technologies.
Like other tech innovations, the gaming industry thrives on constant innovation, with new updates in speed and performance driving the market forward year after year. Thanks to the development of technologies like Ray Tracing in 3D rendering, which traces the reflection of light in a given scene, graphics in high-end AAA gaming are becoming hyper realistic and increasingly immersive.
Ray tracing enables the collection of light information to determine the color of each pixel through real-time calculation. This kind of calculation requires near-simultaneous computation of substantial amounts of data—between 60 à 140 pages worth for one second of an in-game scene. Quoi de plus, display quality is rising fast, with resolutions rapidly transitioning from 4K to 8K standard, while frame buffers are increasing to expand two times more than existing ones in response. That’s why high capacity and high bandwidth are essential to meeting the growing memory demand as games continue to develop.
Developing ‘GDDR6W’ Graphics Memory, with Doubled Capacity and Performance Based on the Cutting-edge Fan-Out Wafer-Level Packaging (FOWLP) La technologie
Haute performance, high capacity and high bandwidth memory solutions are helping bring the virtual realm to a closer match with reality. To meet this growing market demand, Samsung Electronics has developed GDDR6W (x64): the industry’s first next-generation graphics DRAM technology.
GDDR6W builds on Samsung’s GDDR6 (x32) products by introducing a Fan-Out Wafer-Level Packaging (FOWLP) La technologie, drastically increasing memory bandwidth and capacity.
Since its launch, GDDR6 has already seen significant improvements. Juillet dernier, Samsung developed a 24 Mémoire GDDR6 Gbit/s, the industry’s fastest graphics DRAM. GDDR6W doubles that bandwidth (performance) and capacity while remaining the identical size of GDDR6. Thanks to the unchanged footprint, new memory chips can easily be put into the same production processes customers have used for GDDR6, with the use of the FOWLP construction and stacking technology, cutting manufacturing time and costs.
As shown in the picture below, since it can be equipped with twice as many memory chips in an identical size package, the graphic DRAM capacity has increased from 16Gb to 32Gb, while bandwidth and the number of I/Os has doubled from 32 à 64. In other words, the area required for memory has been reduced 50% compared to previous models.
Généralement, the size of a package increases as more chips are stacked. But there are physical factors that limit the maximum height of a package. Quoi de plus, though stacking chips increases capacity, there is a trade-off in heat dissipation and performance. In order to overcome these trade-offs, we’ve applied our FOWLP technology to GDDR6W.
FOWLP technology directly mounts memory die on a silicon wafer, instead of a PCB. Ce faisant,, RDL (Re-distribution layer) technology is applied, enabling much finer wiring patterns. Additionally, as there’s no PCB involved, it reduces the thickness of the package and improves heat dissipation.
The height of the FOWLP-based GDDR6W is 0.7 mm – 36% slimmer than the previous package with a height of 1.1 mm. And despite the chip being multi-layered, it still offers the same thermal properties and performance as the existing GDDR6. Unlike GDDR6, cependant, the bandwidth of the FOWLP-based GDDR6W can be doubled thanks to the expanded I/O per single package.
Packaging refers to the process of cutting fabricated wafers into semiconductor shapes or connecting wires. In the industry, this is known as a ‘back-end process.’ While the semiconductor industry has continuously developed towards scaling circuits as much as possible during the front-end process, packaging technology is becoming more and more important as the industry approaches the physical limits of chip sizes limits. That’s why Samsung is using its 3D IC package technology in GDDR6W, creating a single package by stacking a variety of chips in a wafer state. This is one of many innovations planned to make advanced packaging for GDDR6W faster and more efficient.
The newly developed GDDR6W technology can support HBM-level bandwidth at a system level. HBM2E has a system-level bandwidth of 1.6 TB/s based on 4K system-level I/O and a 3.2 Gbps transmission rate per pin. GDDR6W, de l'autre côté, can produce a bandwidth of 1.4 TB/s based on 512 system-level I/O and a transmission rate of 22Gpbs per pin. Furthermore, since GDDR6W reduces the number of I/O to about 1/8 compared with using HBM2E, it removes the necessity of using microbumps. That makes it more cost-effective without the need for an interposer layer.
“By applying an advanced packaging technology to GDDR6, GDDR6W delivers twice the memory capacity and performance of similar-sized packages,” said CheolMin Park, Vice President of New Business Planning, Samsung Electronics Memory Business. “With GDDR6W, we’re able to foster differentiated memory products that can satisfy various customer needs – a major step towards securing our leadership in the market.”
Samsung Electronics completed the JEDEC standardization for GDDR6W products in the second quarter of this year. It has also announced that it will expand the application of GDDR6W to small form factor devices such as notebooks as well as new high-performance accelerators used for AI and HPC applications, through cooperation with its GPU partners.