Blog dal vivo dell'evento AMD Accelerated Data Center
Primo, la società potrebbe annunciare l'EPYC “Milano-X” linea di processori per server che sfruttano la memoria 3D Infinity Cache, una triplicazione della quantità di cache L3 per i processori, which the company claims significantly improves performance of memory-intensive applications. This should also give you an idea if any upcoming Ryzen desktop processor based on the refreshed chiplet could live up to its claim of “fino 15% gaming performance boost.” The next-generation Instinct MI200 series compute accelerators are equally important as the bring the CDNA2 compute architecture to centerstage, taking the competition to NVIDIA’s A-series Tensor Core processors, and Intel’s upcoming “Ponte Vecchio” Xe-HPC accelerators. As the stream goes begins in 1 hour from now, we will go live.
15:59 UTC: It’s time to get the show on the road, as CEO Dr Lisa Su takes center-stage.
16:02 UTC: AMD categorizes the four workloads dominating datacenters today.
16:04 UTC: New cores, new packaging tech, new CPUs and GPUs
16:05 UTC: New EPYC processor reveal, all new socket
16:06 UTC: Meta si unisce all'ecosistema di cloud computing AMD EPYC
16:06 UTC: Sembra una nuova presa di sicuro
16:07 UTC: Chiplet con 3D Infinity Cache confermati
16:08 UTC: Tecnologia del chipset TSMC 3D sfruttata per 3D Infinity Cache
16:09 UTC: AMD Milano-X EPYC, presa esistente, con un massimo di 64 nuclei, ma un mammut 804 MB di cache per socket
16:10 UTC: Completamente compatibile con le piattaforme SP3 con un aggiornamento UEFI,
16:11 UTC: Prima vista della cache 3D V su AMD EPYC
16:12 UTC: Informatica tecnica al centro di questo processore. Applicazioni ad alta intensità di memoria.
16:12 UTC: 96 MB di cache L3 per chiplet riduce significativamente le latenze del sottosistema di memoria
16:13 UTC: Carico di verifica EDA 66% più veloce della soluzione Intel concorrente
16:15 UTC:
16:15 UTC: 3La cache DV influisce su un'ampia gamma di applicazioni di elaborazione
16:16 UTC: Azzurro al debutto “Milano-X” istanze alimentate dal processore.
16:18 UTC: Q1-2022 disponibilità generale di Milan-X
16:20 UTC: Passiamo ora ai processori di calcolo CDNA2.
16:20 UTC: Istinto MI200. 20% prestazioni HPC più veloci e 4,9 volte più veloci rispetto a “concorrenza.”
16:22 UTC: 58 miliardi di transistor, TSMC 6 nm, 220 unità di calcolo, 128 GB di memoria HBM2E
16:23 UTC: Two form-factors MI200 comes in.
16:23 UTC: AMD just beat Intel to multi-die GPUs, since Intel canned Xe-HP
16:24 UTC: Performance claims:
16:25 UTC: 3.2 TB/s memory bandwidth.
16:26 UTC: More competitive performance claims
16:28 UTC: Debuting 3rd Gen Infinity Fabric, 800 GB/s aggregate bandwidth, and memory coherence
Aggiornare 16:29 UTC: First picture of Oakridge National Labs Frontier, first exascale supercomputer:
16:34 UTC: Genova, is Zen 4-based, built on 5 nm, AMD claims that Genoa will be the “highest performance processor for gen-purpose compute”
16:35 UTC: Up to 96 nuclei, PCIe gen 5, CXL, Memoria DDR5
16:36 UTC: Zen4c is optimized for scale-out cloud performance, “Bergamo” EPYC processor with 128 nuclei, same I/O as “Genova”
16:37 UTC: Updated roadmap
16:38 UTC: And that’s a wrap. A spritely series of major updates that should shake things up in the Intel camp. The core count increase to 96~128, along with the expected generational IPC increase, and next-gen I/O could be AMD’s play against the Xeon “Sapphire Rapids.” Thanks for joining us.