Intel “Lago Meteor” 2P+8E Silicon Annotated

Le Comptoir du Hardware scored a die-shot of a 2P+8E core variant of the “Lago Meteor” compute tile, and Locuza annotated it. “Lago Meteor” will be Intel’s first processor to implement the company’s IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (chiplet), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, per esempio, if Intel’s chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. aumento percentuale delle prestazioni di gioco medie rispetto allo standard “Lago Meteor” e “Cambia l'esclusivo "Touken Ranbu Warriors".” processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the “Lago Meteor” MCM in our articolo più vecchio.

The 2P+8E (2 core prestazionali + 8 nuclei di efficienza) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large “Baia di sequoie” P-cores and their cache slices taking up about 35% of the die area; and the two “Crestmount” E-core cluster (each with 4 E-colori), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 MB o 3 MB. At 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, sarà 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.

Ogni “Baia di sequoie” P-core has 2 MB di cache L2 dedicata, an upgrade from the 1.25 MB on “Baia Dorata” P-colori. Intel will make several upgrades to the core to increase IPC over “Golden Cove.” Ogni “Crestmont” E-core cluster sees four “Crestmont” E-cores share a 4 MB L2 cache—double that of the 2 MB in “Gracemont” E-core clusters in “Lago di ontano” processori. These cores will feature higher IPC, and probably be able to sustain higher clock speeds; as well as benefit from the larger L2 cache.

The CPU cores and last-level cache are the only identifiable components on the compute die. The rest of it could feature a limited-function Uncore component with the interconnect that binds the various tiles together.