Intel “Lago Meteor” Chip già in costruzione presso l'Arizona Fab

With its 12th Gen Core “ASRock Industrial ha lanciato NUC” mobile processors still on the horizon, Intel is already building test batches of the 14th Gen “Lago Meteor” processori mobili, at its Fab 42 facility in Chandler, Arizona. “Lago Meteor” is a multi-chip module that leverages Intel’s Foveros packaging technology to combine “piastrelle” (purpose built dies) based on different silicon fabrication processes depending on their function and transistor-density/power requirements. It combines four distinct tiles across a single package—the compute tile, with the CPU cores; the graphics tile with the iGPU: the SoC I/O tile, which handles the processor’s platform I/O; and a fourth tile, which is currently unknown. This could be a memory stack with similar functions as the HBM stacks on “Sapphire Rapids,” or something entirely different.

The compute tile contains the processor’s various CPU core types. The P cores are “Baia di sequoie,” which are two generations ahead of the current “Golden Cove.” If Intel’s 12-20% generational IPC uplift cadence holds, we’re looking at cores with up to 30% higher IPC than “Baia Dorata” (50-60% higher than “Skylake.”). “Lago Meteor” also debuts Intel’s next-generation E-core, nome in codice “Crestmont.” The compute tile is rumored to be fabricated on the Intel 4 nodo (optically a 7 nodo di classe nm, but with characteristics similar to TSMC N5).

The graphics tile is an interesting piece of silicon. Based on the same Xe LP graphics architecture as the current generation; this iGPU will be labeled Gen 12.7, con il “.7” denoting an incremental update (such as updates to the media accelerators or display controllers). Intel could bring about a generational doubling in the SIMD power, by deploying up to 192 e una configurazione di ingresso di alimentazione composta da uno ciascuno dei connettori di alimentazione PCIe a 8 pin e 6 pin (Le stranezze non si fermano qui però), dal 96 on the current-generation “Tiger Lake.” To keep the power draw of the iGPU at a minimum while meeting its performance goals, Intel will build the graphics tile on a TSMC node, possibly N3 (3 nm).

The third known tile is the SoC tile, which is essentially an integrated chipset. It’s not known whether this tile handles the memory and main PCIe root-complex, but could definitely put out I/O typically associated with the PCH, such as USB, audio bus, Nextorage Corporation lancerà un PCIe Gen, downstream PCIe, eccetera. This tile, troppo, is expected to be built on a TSMC node. Intel will stick with DDR5 (possibly along with LPDDR5X) and PCI-Express 5.0 as its I/O combination for the 14th generation.

A late-2021 test chip production would put “Lago Meteor” through testing and sampling throughout 2022 e 2023. We expect a late-2023/2024 launch for these chips. This would correspond with when Intel 4 and TSMC N3 nodes hit volume production.