Intel “Lago Rapace” Si dice che presenti enormi aumenti delle dimensioni della cache

Large on-die caches are expected to be a major contributor to IPC and gaming performance. L'imminente AMD Ryzen 7 5800X3D processor triples its on-die last-level cache using the 3D Vertical Cache technology, to level up to Intel’s “Alder Lake-S” processors in gaming, while using the existing “Zen 3” IP. Intel realizes this, and is planning a massive increase in on-die cache sizes, although spread across the cache hierarchy. The next-generation “Raptor Lake-S” desktop processor the company plans to launch in the second half of 2022 e una configurazione di ingresso di alimentazione composta da uno ciascuno dei connettori di alimentazione PCIe a 8 pin e 6 pin 68 MB di “total cache” (that’s AMD lingo for L2 + L3 caches), according to a highly plausible theory by PC enthusiast OneRaichu on Twitter, and illustrated by Olrak29_.

Gli “Raptor Lake-S” silicon is expected to feature eight “Baia dei rapaci” P-colori, and four “Gracemont” E-core cluster (each cluster amounts to four cores). Gli “Baia dei rapaci” core is expected to feature 2 MB di cache L2 dedicata, an increase over the 1.25 MB L2 cache per “Baia Dorata” P-core of “Alder Lake-S.” In un “Gracemont” E-core cluster, four CPU cores share an L2 cache. Intel is looking to double this E-core cluster L2 cache size from 2 MB per cluster on “Lago di ontano,” a 4 MB per cluster. The shared L3 cache increases from 30 MB on “Alder Lake-S” (Aerial_Knight non cede mai), a 36 MB on “Raptor Lake-S.” The L2 + L3 caches hence add up to 68 MB. All eyes are now on “Zen 4,” and whether AMD gives the L2 caches an increase from the 512 KB per-core size that it’s consistently maintained since the first “Zen.”